The x86 family of personal computers is well established in the marketplace. Computer manufacturers strive to design the highest performing systems at the lowest cost. However, often the highest performing or lowest cost parts from which a computer can be built are not PC-compatible. If a computer is not PC compatible, the sales market for the computer is severely diminished, thus PC-compatibility is very desirable. Currently, PC systems designers are limited in their ability to build systems that do not conform to PC hardware standards. The reason for the limitation is that much of the existing software that runs on PC's makes explicit assumptions about the nature of the hardware. If the hardware provided by the systems designer does not conform to those standards, many software programs will not be usable. This limits the systems designer's ability to reduce costs and improve functionality.
Currently, the most common means of running the software on a non-compatible machine is to use a software program that does complete emulation of a PC. The emulation is performed on each instruction. This method is practical only for machines that are not binary compatible with x86 PC's because performance is poor.
One prior approach to using non-standard hardware devices provided hardware circuitry to trap and store each bus access to a standard PC device and then cause the execution of an interrupt. The invoked interrupt handler then determined the accessed address from the hardware circuitry, converted this to the proper device address and executed that operation. This technique worked adequately when the processor and system were relatively simple and only for certain operating systems. However, it is not practical on current computer systems because of increased complexity of the processor, system and operating systems and the frequent unavailability of an interrupt.
This interrupt problem could be solved by the use of System Management Mode (SMM) found in certain processors, such as the Intel 486SL, 486 S-class and Pentium microprocessors. The SMI interrupt cannot be masked by software and therefore is always available to the system manufacturer. However, there are several disadvantages to the current SMM implementations for doing hardware emulation. The first is that entry to and exit from SMM requires many processor cycles. This is because SMM implementations were done with the assumption that the only thing that would be done in SMM is power management. This assumption caused the SMM implementor to design the processors so that the full state of the processor was saved on entry to SMM and the full state of the processor was restored on exit from SMM. These operations require 100's of processor cycles. This entry/exit overhead of current SMM implementations greatly limits it's usefulness for emulation.
A second disadvantage is that while in SMM access to user memory is limited and/or cumbersome because of the different modes of operation and their corresponding addressing mechanisms. In this context, user memory is memory that is used by programs when the processor is operating in one of its operating modes. In the 386 family of microprocessor, three different operating modes exist in addition to SMM. Real mode is the default mode of operation for the microprocessor and is provided for backwards compatibility with the earlier 8086 and 8088 processors. Protected mode was first introduced in the 80286 microprocessor and improved in the 386 microprocessor. Protected mode removes most of the memory management limitations of the earlier processors. The preferred mode of operation for the 386 processor is its protected mode. Once the processor is in protected mode, an additional real mode environment, called virtual 8086 mode, can be created for backward compatibility with real mode applications. Memory management in the processor is performed by a segmentation unit and a paging unit. Real mode utilizes a 16-bit selector, shifted left four bits, and a 16-bit offset to produce a 20-bit address for addressing up to 1MB of memory. The 16-bit offset limits the segment to a maximum of 64k of memory. In protected mode the segment register is redefined as a selector which points to a 32-bit segment base address and the offset is increased to 32 bits, with the segment base address and the offset simply being added to provide the linear address. Protected mode may enjoy a 4GB maximum memory segment. If paging is enabled, the linear address is then translated by the paging unit into a physical address. Paging is a mechanism to support a large physical address space in memory using a small amount of memory and some hard disk space. Virtual 8086 mode addressing is similar to real mode in that the same 16-bit selector and offset are used, however, it is different from real mode in that the 1MB address range can be placed anywhere within the 32-bit protected mode addressing range. Thus, three different addressing schemes may exist in a computer system using a 386 compatible processor. When the processor switches to system management mode, a fourth hybrid addressing mechanism is utilized. SMM generally uses a 32-bit flat memory model addressing scheme. Segment register values are stilled shifted 4 bits and added to the offset values, but both can be 32 bit values.
In a 386 compatible processor, addressing mechanisms cannot be mixed between different modes of operation. For example, when the processor is operating in 32-bit protected mode and then switches to 16-bit real mode, no protected mode addressing selectors or offsets can be directly used. To access a protected mode address space with a real mode addressing mechanism, the entire protected mode addressing mechanism including selectors, offsets, and paging must be calculated. Such is the case between any two addressing modes. This limitation complicates device emulation when using SMM because the SMM code must devote significant amounts of time in an address translation process which converts the address used by the user program into an address that SMM can use to access the same memory location. This process is complicated by the fact that the x86 architecture supports several different addressing modes so that the SMM code must analyze the operational mode of the user program and select an address conversion algorithm that is appropriate to that mode. So this addressing mode change in SMM further exacerbates the overhead problems, so that use of the SMI is not readily feasible.
Thus, it is desirable to have a processor that can provide emulation transparently to the operating system and application software while using the built-in memory management features but using very few processor cycles to enter and exit the emulation operations and not having large address translation burdens.